This application claims priority from Korean Patent Application No. 2001-30384, filed on May 31, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to a nonvolatile semiconductor memory device and, more particularly, to a flash memory device capable of checking memory cells with a progressive fail characteristic.
Many nonvolatile semiconductor memory devices are flash memory devices having a plurality of memory cells arranged in a matrix of rows and columns. The flash memory device is capable of erasing an array of memory cells at the same time, and provides an ability to electrically program or read out information of one or more memory cells in the array.
The memory cells of the flash memory device generally use floating gate transistors arranged with rows and columns. Each of the floating gate transistors has a source, a drain, a floating gate, and a control gate. A conventional flash memory cell is shown in FIG. 1. In that figure, a flash memory cell includes source and drain regions 2 and 3 formed in a P-type semiconductor substrate (or bulk) 1, a floating gate 6 formed over a channel region 5 between the source and drain regions 2 and 3, and a control gate 8 formed over the floating gate 6. A thin insulating film 4 having a thickness of about 100 xc3x85 is formed between the channel region 5 and the floating gate 6, and another insulating film 7 is formed between the floating gate 6 and the control gate 8. The control gate is connected to a wordline.
The following table shows approximate source, drain, control gate, and bulk voltages based upon program, read, and erase operations of a conventional flash memory device.
As can be seen in the table, a flash memory cell is programmed by applying a ground voltage of 0V to the source region 2 and the semiconductor substrate 1, applying a high voltage of about 9V to the control gate, and applying a voltage of 5V capable of generating hot electrons to the drain region 3. Such a program operation is carried out to accumulate sufficient negative charges in the floating gate 6. Thus, the floating gate 8 has a positive potential to heighten a threshold voltage of the flash memory cell in a read operation.
During a read operation wherein a voltage of about 4.5V is applied to the control gate 8 and a ground voltage is applied to the source region 3, a channel region 5 of a threshold voltage heightened (i.e., programmed) memory cell does not become conductive. A current, which would otherwise flow from the drain region 3 through the channel region 5 to the source region 2, is prevented. At this time, the memory cell has an xe2x80x9coffxe2x80x9d state and its threshold voltage is distributed within a range of about 6V to 7V.
Flash memory cells existing in any sector are simultaneously erased by F-N tunneling (Fowler-Nordheim tunneling) scheme. According to F-N tunneling scheme, a negative high voltage of about xe2x88x929V is applied to the control gate 8, and a positive voltage of 9V capable of causing F-N tunneling is applied to the semiconductor substrate 1. As shown in the above table, the source and drain regions 2 and 3 are held at a floating state. An erase operation performed according to such a bias condition is called a negative gate and bulk erase (NGBE) operation. Under such a bias condition, a strong electric field of about 6-7 MV/cm is produced between the control gate 8 and the semiconductor substrate 1 to cause F-N tunneling. In other words, the negative charges accumulated in the floating gate 6 are discharged to the semiconductor substrate 1 through the thin insulating film 5 of about 100 xc3x85. Accordingly, the threshold voltage of the flash memory cell is lowered in a later-performed read operation.
Various erase methods associated with a flash memory device are disclosed in U.S. Pat. No. 5,781,477 entitled xe2x80x9cFlash Memory System Having Fast Erase Operationxe2x80x9d, U.S. Pat. No. 5,132,935 entitled xe2x80x9cErase Of EEPROM Memory Arrays To Prevent Over-Erased Cellxe2x80x9d, U.S. Pat. No. 5.220,533 entitled xe2x80x9cMethod And Apparatus For Preventing Overerase In A Flash Cellxe2x80x9d, U.S. Pat. No. 5,513,193 entitled xe2x80x9cNonvolatile Semiconductor Memory Device Capable Of Checking The Threshold Value Of Memory Cellsxe2x80x9d, and U.S. Pat. No. 5,805,501 entitled xe2x80x9cFlash Memory Device With Multiple Checkpoint Erase Logicxe2x80x9d.
After the foregoing NGBE operation is carried out, an erase verify operation is carried out to verify whether all flash memory cells in a sector are within a target threshold voltage range (e.g., 1V to 3V) corresponding to an xe2x80x9conxe2x80x9d state. In the erase verify operation, a voltage (erase verify voltage) of about 3V is applied to the control gate 8, and the source region 2 and the semiconductor substrate 1 are grounded. Except for bias conditions, the erase verify operation can be carried out in the same manner as the read operation.
A threshold voltage of an erased flash memory cell is conventionally distributed within a range of 1V to 3V. However, when all memory cells in a sector are erased at the same time, a threshold voltage of some flash memory cells may be lowered to 1V or less. A flash memory cell having a threshold voltage of 1V or less is conventionally called an over-erased flash memory cell, which can be repaired by an erase repair operation for shifting a threshold voltage within a target threshold voltage range (1V to 3V) corresponding to an xe2x80x9conxe2x80x9d state.
In the erase repair operation, the source region 2 of an over-erased flash memory cell and the semiconductor substrate 1 are grounded, a voltage of about 3V is applied to the control gate 8, and a voltage of 5V is applied to the drain region 3. Under such a bias condition, charges are accumulated in a floating gate 6, but less charge is accumulated than during a program operation. Therefore, the foregoing erase repair operation is carried out to shift a threshold voltage of an over-erased flash memory cell back to within the target threshold voltage range (1V to 3V).
After the erase and erase repair operations are completed, failed memory cells may be replaced with spare cells using a conventional redundancy technique. A current-voltage curve of an erased flash memory cell is shown in FIG. 2. A curve xe2x80x9c10xe2x80x9d is a current-voltage curve of a memory cell having the lowest threshold voltage (e.g., 1V), and a curve xe2x80x9c12xe2x80x9d is a current-voltage curve of a memory cell having the highest threshold voltage (e.g., 3V). A current-voltage curve of normally erased memory cells may exist between the curves xe2x80x9c10xe2x80x9d and xe2x80x9c12xe2x80x9d. This curve will be referred to as a xe2x80x9cnormal voltage-current curvexe2x80x9d hereinafter. As shown in FIG. 2, there is little or no difference between the slopes of current-voltage curves corresponding to erased cells (i.e., on-cells).
Because of processing problems, there may be a memory cell having a current-voltage curve whose slope is different from that of the normal current-voltage curve. This current-voltage curve will be referred to as an xe2x80x9cabnormal current-voltage curvexe2x80x9d hereinafter. If a slope of a current-voltage curve is considerably great, a memory cell having the slope is detected by the foregoing erase operation to be replaced using a conventional redundancy technique. However, if the slope of the current-voltage curve is not great, a normal read or write operation can be carried out, at least during the testing phase. For example, when a wordline voltage VREAD is applied to a memory cell having a curve xe2x80x9c14xe2x80x9d, an amount of a cell current flowing through the memory cell is larger compared with a reference current. This means that the memory cell having the abnormal current-voltage curve xe2x80x9c14xe2x80x9d is normally determined as an xe2x80x9con-cellxe2x80x9d, and will not be replaced, even though it is a potentially defective cell.
If read and write operations are repeated in the potentially defective cell, a hole trap can be created at an insulator covering a floating gate to cause a charge loss of the floating gate. As a result, a memory cell having an abnormal current-voltage curve is changed in a coupling ratio, or a threshold voltage of the memory cell shifts. For example, the cell having the current-voltage curve xe2x80x9c14xe2x80x9d is changed to a current-voltage curve xe2x80x9c16xe2x80x9d, as shown in FIG. 2. If a wordline voltage VREAD is applied to a memory cell having the current-voltage curve xe2x80x9c16xe2x80x9d, the amount of a cell current flowing through the memory cell is smaller than a reference current IREF, thus making a read failure. That is, a read failure in the defective cell causes a deterioration of reliability and endurance of the entire device.
The present invention addresses this and other limitations in the prior art.
Embodiments of the invention include a NOR-type flash memory device capable of checking a progressive fail characteristic. Nonvolatile semiconductor memory devices according to embodiments of the present invention support an erase verify operation mode and a test verify operation mode. The erase verify operation mode determines whether an erased memory cell is lower than a maximal threshold voltage (e.g., 3V), and the test verify operation mode determines whether an erased memory cell has a progressive fail characteristic.
In some of the embodiments, once the memory device enters the test verify operation mode, a wordline voltage to be applied to a memory cell and a reference wordline voltage to be applied to a reference cell are generated. The wordline voltage and the reference wordline voltage generated in the test verify operation mode are set to be higher than those generated in the erase verify operation mode. Therefore, a current flowing through the memory cell and the reference cell is increased to check a memory cell with a progressive (or potential) fail characteristic.